6.5080 Multicore Programming Extra Quality May 2026

Before writing a single parallel loop, 6.5080 insists on understanding the hardware. Multicore processors do not provide a “perfectly simultaneous” view of memory. Instead, each core possesses private L1 and L2 caches, a shared L3 cache, and the main DRAM. This hierarchy introduces the problem of . The course covers the MESI (Modified, Exclusive, Shared, Invalid) protocol extensively. A student learns why two threads incrementing the same shared variable from different cores can miss each other’s updates, leading to lost counts.

Recognizing that locks have fundamental limits (blocking, priority inversion, and convoying), 6.5080 introduces non-blocking synchronization. Students implement a lock-free stack using operations. They learn the ABA problem (a pointer changes from A to B and back to A, fooling the CAS) and solve it with tagged pointers or double-word CAS. 6.5080 multicore programming

Mastering Concurrency: The Principles and Practices of 6.5080 Multicore Programming Before writing a single parallel loop, 6

6.5080 Institution: (Contextualized as an advanced graduate/upper-level undergraduate course in Computer Science) Date: April 13, 2026 This hierarchy introduces the problem of

The most contemporary module covers (TM). Both hardware (HTM on Intel TSX) and software (STM) implementations are examined. Students write code where critical sections are marked as atomic transactions. The system optimistically executes the code and aborts if a conflict is detected. This dramatically simplifies reasoning (no deadlock, no lock ordering), but introduces new challenges: transaction size limits, irrevocable actions, and performance collapse under contention. Through benchmarking, the course concludes that while TM is not a universal silver bullet, it excels for complex composite operations (e.g., transferring money between two bank accounts) where fine-grained locking would be a nightmare.